In recent years, there has been a strong tendency toward reduced size in electronic devices, and progress has been made in enhancing functional integration and accelerating signal processing speeds. In association with this, the wiring of semiconductor chips has become thinner and the insulating layers and wiring layers of semiconductor chips have become more fragile. Furthermore, electrode pitches of 100 μm or less have come to be demanded.
As shown in FIG. 10B, in a semiconductor device which has a semiconductor chip 3 flip-flop mounted onto a wire electrode 2 formed on a substrate 1, a bump electrode 4 formed on the surface of the semiconductor chip 3 is abutted against and electrically connected with the wire electrode 2 and in this state, a thermosetting resin 5 is cured and the position of the semiconductor chip 3 on the substrate 1 is fixed.
More specifically, as shown in FIG. 10A, a wafer on which an electronic circuit is built (not illustrated) is mounted on the semiconductor chip 3, and the bump electrode 4 is formed on an electrode pad 6 which is formed on the surface of the semiconductor chip 3. The bump electrode 4 is formed entirely of gold (Au) which is relatively deformable. The thermosetting resin 5 is applied as an underfill resin to the mounting position of the substrate 1, and the semiconductor chip 3 is pressed against the substrate 1 with the bump electrode 4 facing toward the substrate 1, and the bump electrode 4 is abutted against and electrically connected with the wire electrode 2, in addition to which the shape of the front end thereof is deformed. Moreover, by heating the semiconductor chip 3 by means of a heating tool 7 via a separating sheet 8, in a state where the semiconductor chip 3 is pressed against the substrate 1, the thermosetting resin 5 is cured and fixing is completed.
However, if warping occurs as shown in FIG. 11 in the semiconductor chip 3 after mounting, then a gap 9 arises between the bump electrode 4 and the wire electrode 2, thus giving rise to a connection defect.
It is technically very difficult to mount a semiconductor chip on a wiring substrate using a bump electrode in the case of fragile wiring layers and narrow electrodes which result when the electrode pitch is made narrow. Structures and methods which enable easy assembling even under low load and with narrow pitch have been discussed.
Therefore, Patent Document 1 describes a semiconductor chip 3 wherein, instead of the bump electrode 4 which is formed entirely of gold (Au), a vertically long core 10 made of an insulating material is provided on an electrode pad 6 and a metal film 11 is provided from the surface of the core 10 through to the electrode pad 6.
A semiconductor device in which this semiconductor chip 3 is flip-chip mounted on a substrate 1 is assembled as shown in FIG. 12B and FIG. 12C.
In FIG. 12B, similarly to FIG. 10A and FIG. 10B, by pressing the semiconductor chip 3 against a wire electrode 2 by means of a heat tool 7, the electrode pad 6 is electrically connected with the wire electrode 2 via the metal film 11, and furthermore, by means of this pressing action, elastic deformation is caused so that the height of the core 10 which has had a vertically long shape becomes lower. By heating the thermosetting resin 5 to a curing temperature or higher in this state, the thermosetting resin 5 is cured and the position of the semiconductor chip 3 on the substrate 1 is fixed.
Patent Document 2 describes a semiconductor chip 3 in which an elastic body 20 is formed on an electrode pad 6 as shown in FIG. 13 and a bump electrode 21 is formed thereon.
Technology whereby a semiconductor chip 3 is connected by soldering to a substrate 25, rather than pressing a semiconductor chip 3 against a substrate 1 and in this state electrically connecting the same by curing a thermosetting resin 5, is described in Patent Document 3. As shown in FIG. 14, the semiconductor chip 3 is connected by soldering to a pad 26 of the substrate 25, and a pier 28 made of copper plating is formed on an insulating layer 27 between a pad 6 of the semiconductor chip 3 and low-melting-point solder 23. Resin 29 is filled inside the pier 28. The pad 6 of the semiconductor chip 3 is connected by soldering to the pad 26 of the substrate 25 via a lid 30 which is created by the pier 28 and the plating, and via the low-melting-point solder 23.
Patent Document 1: Japanese Patent Application Laid-Open Publication No. H3-62927 (FIG. 2)
Patent Document 2: Japanese Patent Application Laid-Open Publication No. H1-233741 (FIG. 1)
Patent Document 3: Japanese Patent Application Laid-Open Publication No. 2000-174050 (FIG. 17)